In the related art, the bit cost of a NAND-type flash memory was reduced by increasing a degree of integration by miniaturizing the planar structure thereof. In recent years, a technology for further increasing the degree of integration by three-dimensionally stacking memory cells has been suggested. In such a stacked memory device, when the degree of integration is further increased, how to lead out wiring from the memory cell and connect the wiring to an external circuit or a peripheral circuit becomes an issue.